1. Technical Field
Example embodiments relate to a multi-chip package and a method of manufacturing the same. More particularly, example embodiments relate to a multi-chip package including a plurality of semiconductor chip sequentially stacked, and a method of manufacturing the multi-chip package.
2. Description of the Related Art
Generally, a plurality of semiconductor fabrication processes may be performed on a semiconductor substrate to form a plurality of semiconductor chips. In order to mount the semiconductor chips on a printed circuit board (PCB), a packaging process may be performed on the semiconductor chips to form semiconductor packages.
In order to increase a storage capacity of the semiconductor package, a multi-chip package including a plurality of the semiconductor chip sequentially stacked have been developed. The semiconductor chips of the multi-chip package may have substantially the same size or different sizes. Further, the semiconductor chips having the same size may be crosswise stacked. When the semiconductor chips may have the different sizes, an upper semiconductor chip may have a size larger than that of a lower semiconductor chip.
Therefore, the upper semiconductor chip may have a protrusion overhanging an area beyond both side surfaces of the lower semiconductor chip. Because the protrusion of the upper semiconductor chip may not be supported by the lower semiconductor chip, the protrusion may be deflected. Particularly, bonding pads of the upper semiconductor chips may be arranged on an upper surface of the protrusion. Thus, wire bonding failures may be generated due to the deflected protrusion. That is, a bonding wire may not be accurately connected to the bonding pads on the deflected protrusion.
Further, a sufficient amount of a molding member may not be provided between the deflected protrusion and a package substrate. Thus, voids may be generated in the molding member between the deflected protrusion and the package substrate.